1. Field of the Invention
The present invention generally relates to transmitter-receivers and, more particularly, to a transmitter-receiver of TDMA/TDD (time division multiple access/time division duplex) system in which transmission and reception are effected at different times or in a time-division manner.
2. Description of the Prior Art
In a TDMA/TDD system transmitter-receiver utilized in a telepoint system or the like, a transmission frequency and a reception frequency are the same. As shown in FIG. 1 of the accompanying drawings, transmission slots T1 to T4 and reception slots R1 to R4 constitute one frame and the slots T1, R1; T2, R2; T3, R3; and T4, R4 are utilized in pairs.
According to the above transmission and reception system, the transmission and reception are effected in the transmission slots and the reception slots in a time division fashion so that the transmission frequency and the reception frequency can be made the same. Therefore, each transmission channel can be utilized highly efficiently. When this transmission and reception system is applied to a cordless telephone apparatus, for example, plural sets of cordless telephone apparatus can utilize the same frequency and a telephone conversation can be made by many cordless telephone apparatus simultaneously.
A transmitting circuit and a receiving circuit in the above TDMA/TDD system transmitter-receiver that effects the above transmission and reception are arranged as shown in FIG. 2 of the accompanying drawings.
In FIG. 2, reference numeral 10 generally depicts a transmitting circuit and reference numeral 20 generally depicts a receiving circuit. As shown in FIG. 2, in the transmitting circuit 10, an audio signal is supplied from an input terminal 11 to a digital transmission processor circuit 12, in which the audio signal is processed in such a fashion as to effect the TDMA/TDD system transmission. The audio signal thus processed is delivered at every transmission slot T1, for example.
The base band transmission signal from the digital transmission processor circuit 12 is supplied to a modulator circuit 13, in which the signal is modulated to a predetermined intermediate frequency signal f.sub.1. It is customary that the modulator circuit 13 employs a phase-locked loop (PLL) circuit in its modulation. Therefore, under the control of the PLL circuit, there is obtained a signal frequency-modulated by a carrier signal (intermediate frequency signal f.sub.1). The intermediate frequency signal f.sub.1 output from the modulator circuit 13 is supplied to a mixer 14.
A frequency signal f.sub.2 (hereinafter this frequency signal f.sub.2 will be referred to as a channel selecting signal) output from a PLL frequency synthesizer 31 formed of a PLL circuit is supplied to the mixer 14. Then, the mixer 14 mixes the channel selecting signal f.sub.2 with the intermediate frequency signal f.sub.1 to provide a signal f.sub.3 having a transmission frequency. The transmission signal f.sub.3 having the transmission frequency is supplied through an amplifier 15, a bandpass filter 16 and a high frequency switch circuit 32 to an antenna 33. Then, the transmission signal f.sub.3 is transmitted from the antenna 33. The channel selecting signal is a signal whose frequency is changed in response to a frequency of a transmission-reception channel.
In the receiving circuit 20, a signal transmitted during the reception slot R1 is received at the antenna 33. A frequency of the received signal and a frequency of the transmitted signal transmitted from the transmitting circuit 10 are equal to each other.
The received signal f.sub.3 is supplied through the high frequency switch circuit 32, a bandpass filter 21 and an amplifier 21 to a mixer 23. Then, the channel selecting signal f.sub.2 from the PLL frequency synthesizer 31 is supplied to the mixer 23 and the channel selecting signal f.sub.2 is mixed to the received signal by the mixer 23, thereby converted into the intermediate frequency signal f.sub.1 (first intermediate frequency signal). The first intermediate frequency signal f.sub.1 is supplied through a bandpass filter 24 to a mixer 25. An oscillation signal f.sub.4 having a constant frequency output from a local oscillator 26 is supplied to the mixer 25, in which the signal f.sub.4 is mixed with the signal f.sub.1 to provide a second intermediate frequency signal f.sub.5. This second intermediate frequency signal f.sub.5 is supplied through a bandpass filter 27 to a demodulator circuit 28, in which the signal modulated transmission is demodulated. Then, the demodulated signal is supplied to a digital reception processor circuit 29, in which it is processed in such a fashion as to become able to be received by the TDMA/TDD system. The audio signal thus processed is delivered to an output terminal 30.
The TDMA/TDD system transmitter-receiver shown in FIG. 2 makes effective use of the fact that the transmission frequency and the reception frequency are equal to each other. Therefore, one frequency synthesizer 31 can serve as both the transmission channel selecting signal generator circuit in the transmitting circuit 10 and the reception channel selecting signal generator circuit in the receiving circuit 20.
When the transmission and reception channel selecting frequency synthesizer is shared by the transmitting circuit and the receiving circuit, however, the intermediate frequency signal output from the modulator circuit 13 of the transmitting circuit 10 and the intermediate frequency signal (first intermediate frequency signal) output from the mixer 23 of the receiving circuit 20 have the same frequency f.sub.1. If the frequencies treated by both the circuits 10 and 20 are the same, there is then the disadvantage such that the receiving side 20 is disturbed by the intermediate frequency signal from the transmitting circuit 10.
To avoid the receiving circuit 20 from being disturbed, it is proposed that a transmission channel selecting frequency synthesizer and a reception channel selecting frequency synthesizer are separately provided to change frequencies of intermediate signals of the transmitting circuit 10 and the receiving circuit 20. Since, however, the PLL type frequency synthesizer is relatively complex in arrangement, it is not desirable that one transmitter-receiver includes two PLL type frequency synthesizers from a standpoint of a manufacturing cost, an installation space, a consumed amount of electric power or the like.
Also, it is proposed that an oscillation frequency of one frequency synthesizer is changed in the transmission slot and the reception slot so that the intermediate frequency in the transmitting circuit 10 and the intermediate frequency in the receiving circuit 20 are changed. However, a time (guard band) between the transmission slot and the reception slot is remarkably small (e.g., 50 .mu.s). Therefore, if a frequency synthesizer is arranged so as to become able to change its oscillation frequency in such a short period of time, then the frequency synthesizer becomes complicated in arrangement.
To prevent a radio interference from taking place when the receiving circuit and the transmitting circuit has the same intermediate frequency, it is proposed that the modulator circuit in the transmitting side is disabled during a period of the reception slot R to thereby prevent the intermediate frequency signal from being formed in the transmitting circuit 10 side during the period of the reception slot R. The PLL circuit needs a lot of time to be stabilized since it has been actuated. Also, the period of the reception slot is as short as about 1 millisecond. Accordingly, if the PLL circuit constructing the modulator circuit 13 is disabled during the period of the reception slot R, then the PLL circuit will not be locked substantially until the period of the next transmission slot T.
In a communication system (e.g., cordless telephone system) to which the above-mentioned TDMA/TDD system will be applied in future, it is expected that a very high frequency (e.g., 1 GHz band) is utilized as a transmission frequency. Therefore, it is difficult to construct a modulator circuit having such a high frequency using an oscillating circuit other than the PLL circuit.
Accordingly, although the modulator circuit is constructed by the PLL circuit in the TDMA/TDD system, the operation of the PLL circuit cannot be substantially stopped during the period of the reception slot R as described above. Therefore, the transmitting circuit and the receiving circuit cannot be substantially protected from a radio interference by the control of the modulator circuit.